A simple oxidation technique for quantum dot dimension shrinkage and tunnel barriers generation

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M. Sutikno, U. Hashim, Z.A.Z. Jamal

2008 Microelectronics Journal Vol. 39 Issue 5 Article Cited by 0

Abstract

The tunnel barriers generation and the quantum dot size shrinkage play a significant role in single-electron transistor (SET) fabrication. Because the numerically etch indicators were not found, the technical indicators, high contrast surface and high smoothness surface were used to optimize the etch process. Si nanostructures oxidation using either oxidation furnace or rapid thermal processing (RTP) equipment can result in silicon dioxide (SiO2)-embedded-Si. In this research, we compare the furnace-oxidized-Si nanostructures with the RTP-oxidized-Si nanostructures. The oxidation rate of Si nanostructures using a furnace is 0.36 nm/s, while the oxidation rate of Si nanostructures using RTP is 2.16 nm/s. © 2007 Elsevier Ltd. All rights reserved.

Affiliations

Physics Department, Faculty of Mathematics and Natural Sciences, Universitas Negeri Semarang (UNNES), Gunung Pati, Semarang 50229, Indonesia; Nano Fabrication Cleanroom, School of Microelectronic Engineering, Universiti Malaysia Perlis (UniMAP), Kuala, Perlis, 02000, Malaysia